The present invention relates generally to a method and system for computer aided design (CAD) of integrated circuits and in particular to timing validation of clock tree delays.
Integrated circuit (IC) timing validation has adapted to increasing IC density and complexity. Static timing analysis (STA) is often utilized for performing timing analysis towards validation and optimization of synchronous circuit designs. STA validation allows the designer to make modifications to improve the reliability, efficiency, and/or speed of the circuit design. Design margin or pessimism is generally incorporated into STA so that variations in modeling, design and manufacturing of the IC are taken into account in the design by providing extra time before signals in the IC change in order to guarantee the proper functioning of the IC. Over-design or excess pessimism may cause the IC to have slow speed characteristics, miss speed targets, overly complicate the design, and/or delay finishing the design on time.
Clock trees are a type of circuit path that presents special design challenges because one clock-driver circuit block disposed at the root of the tree may be required to output or source a signal that drives the receiving inputs or clock sinks of thousands of other logic circuit blocks disposed at the leaves of the tree sometimes across the whole IC. In one CAD flow, the clock tree is synthesized automatically including placing a multitude of buffer circuit blocks, hereinafter also referred to as “buffers,” along the clock tree to assist driving the large capacitive load presented at the root by the combination of the long wire lengths and the multitude of clock sinks at the leaves.
Path based analysis (PBA) is a type of STA used to calculate delays beginning at the input and tracing a path to the output of a circuit path. PBA CAD computation may be slow in analyzing circuit designs as each circuit path is analyzed separately. For example, only the slews of the input pins along a given circuit path are considered in PBA analysis. PBA is generally used for optimization when the circuit design is nearly completed due to the exhaustive nature of PBA and the amount of computational time needed to perform PBA. On-chip-variation (OCV) and advanced on chip variation (AOCV) analysis are types of PBA that comprehends statistical variations in logic circuit blocks created during advanced IC manufacturing technology in contrast to systemic variations such as for example slow circuit blocks due to manufacturing the IC with atypically large transistor gate length sometimes occurring in both advanced as well as older generations of IC technology.
AOCV is usually performed on clock trees after clock tree synthesis (CTS) for the reasons described above and may result in excess pessimism in the timing. Thus, there is a need for a better CAD flow that performs AOCV before CTS to reduce excess pessimism in the timing.